In the recent semiconductor processing technology, a challenge to higher integration of large-scale integrated circuits places an increasing demand for miniaturization of circuit patterns. There are increasing demands for further reduction in size of circuit-constructing wiring patterns and for miniaturization of contact hole patterns for cell-constructing inter-layer connections. As a consequence, the manufacture of circuit pattern-written photomasks for use in the photolithography for forming such wiring patterns and contact hole patterns needs a technique capable of accurately writing finer circuit patterns in order to meet the miniaturization demand.
In forming a finer feature pattern, a resist film is exposed to a pattern of radiation using a photomask and an optical system. If the photomask undergoes any shape change at this point, the positional accuracy of the resultant image is reduced, resulting in defective patterns. To overcome the problem, the shape of a photomask substrate must be controlled as reported in JP-A 2003-50458. It is reported that use of a substrate having a specific surface topography as the photomask substrate suppresses any change of surface topography when the photomask is chucked to the mask stage of the exposure tool.
In the prior art, the flatness of photomask-forming transparent substrates and photomask blanks is regarded important. When an optical film such as a light-shielding film or phase shift film is deposited on a photomask-forming transparent substrate, the stress in the optical film is controlled so that the substrate shape may not be changed. Many techniques for controlling “sori” (warpage or bow), that is, shape change of the substrate surface are known, as described in JP-A 2004-199035.
Aside from the problem of substrate shape, the size control of a pattern of optical film such as a semiconductor circuitry pattern written on a photomask is also a problem. A higher degree of control is required as the desired pattern feature size is reduced. For example, in the manufacture of a photomask for use in producing a pattern having the minimum line width of up to 65 nm, especially up to 50 nm, a light-shielding film of chromium base material used in the prior art is difficult to control side etching during the etching step. Then the finish size may widely vary with a different density of a pattern to be written, known as the pattern density dependency or “proximity bias”. JP-A 2007-241060 describes that the problem of proximity bias can be mitigated by forming the light-shielding film from an optionally transition metal-containing silicon base material and that the light-shielding film is processed using a very thin chromium base material as an etching mask. It is described that using an optionally transition metal-containing silicon base material as the etching mask, a photomask which is size controlled at a very high accuracy can be manufactured.
The photomask for use in the lithography wherein a semiconductor circuit pattern has a minimum size of up to 45 nm requires a high degree of size control. When such a photomask is prepared using an optionally transition metal-containing silicon base material as the light-shielding film and a chromium base material as the etching mask film, the size control has little latitude.
In the manufacture of photomasks used in the lithography for forming a pattern having a minimum size of up to 45 nm, especially the lithography of which a higher accuracy of positional control is required as in the case of double patterning (Proceedings of SPIE, Vol. 6153, 615301-1 to 19 (2006)), the yield of photomask manufacture cannot be increased unless a reliability surpassing the currently available accuracy is provided.
Citation ListPatent Document 1:JP-A 2003-050458Patent Document 2:JP-A 2004-199035Patent Document 3:JP-A 2007-241060(US 2007/212619, EP 1832926A2)Patent Document 4:JP-A H07-140635Patent Document 5:JP-A 2007-241065Patent Document 6:JP-A S63-085553Non-Patent Document 1:Proceedings of SPIE, Vol. 6153,615301-1 to 19 (2006)